Implementations of SPARC architecture were at first designed & utilized for workstations, so utilized for big SMP servers produced by Sun Microsystems and Fujitsu among others. SPARC machines come typically synonymous using Solaris, the operating system (OS) from Sun designed for SPARC. Nevertheless various ports from either operating systems prefer NeXTSTEP, Linux, FreeBSD, OpenBSD and NetBSD work on SPARC processors.

There use at times been many revisions of a architecture, the virtually all recent existence versions 8 & 9.

Features

A SPARC architecture was heavy influenced per sooner designs of the RISC We & Deuce from either a University of California, Berkeley. These original RISC designs were minimalist, including when couple of features or even op-codes when conceivable & demanding that 100% operations complete around a single period. This mass produced the two similar to the MIPS architecture in many ways, including a want of videos like multiply or even divide. A second feature of SPARC influenced by this early RISC movement is the branch delay slot.

A SPARC processor unremarkably contains when numbers of when 128 general purpose registers. At any point, exclusively 32 of a children come available - 8 come spherical registers & a more Twenty-four come from either the stack of registers. These Twenty-four registers form what is known as the register window, & at work call/return, this window is moved higher and down the register fold. To each one window has Ogdoad local registers & shares Octonary registers by using adjacent windows. A shared out registers come utilized for passing work parameters & giving values, & a local registers come utilized for keeping values through work calls. A "Scalable" inside SPARC comes from either a fact that a SPARC specification allows as much as 32 windows. Then a implementation might see to implement everthing 32 to provide utmost call for even fold efficiency, or to implement minimum to reduce a context switching period. More architectures that include similar register windows include Intel i960, IA-64, and AMD 29000.

Inside version Eighter, a floating-point register file has 16 double precision registers. Both of the deuce may be utilized when two single precision registers, providing the aggregate of 32 individual preciseness registers. An odd-possibly benumb pair of double preciseness registers may be utilized as a quad precision register, thus letting Eighter quad preciseness registers. Version 9 added Xvi further double preciseness registers, however these extra double preciseness registers may non exist when utilized as lone preciseness registers.

Labelled add & subtract videos perform adds & subtracts in values assuming that a bottom ii bits don't participate in the computation. This may be utile in the implementation of the rerun period for ML, Lisp, and similar languages that will have the labeled whole number format.

History

A architecture has never agaaround across two or three revisions & has gained multiply & divide functionality in version Ogdoad. A virtually all real update resulted in the version Ennead which occurs as 64-bit SPARC specification.

Among various implementations of SPARC, Sun's SuperSPARC & UltraSPARC-I personally were super popular, and then equally to exist when utilized as reference frame for SPEC CPU95 and CPU2000 benchmarks.

|- ! colspan=Fourteen style="background:#efefef;" | SPARC microprocessor specifications |- style="vertical-align: top;" !Model!!Frequency
[Mhz]!!Architecture
Version!!Month!!Run
[µm]!!Electronic transistor
[millions]!!Die size
[mm²]!!IO Diaper pins!!Power
[W]!!Voltage
[V]!!L1 Dcache
[k]!!L1 Icache
[k]!!L2 Cache
[k]!!L3 Cache
[k] |- |microSPARC I||40-50||V8||1992||0.8||0.8||225||288||2.5||5||2||4||none||none |- |SuperSPARC I||33-60||V8||1992||0.8||3.1||--||--||14.3||5||16||20||0-2048||none |- |HyperSPARC A||40-90||V8||1993||0.5||--||--||--||--||5?||0||8||0-128||none |- |microSPARC II||60-125||V8||1994||0.5||2.3||233||321||5||3.3||8||16||none||none |- |HyperSPARC B||90-125||V8||1994||0.4||--||--||--||--||3.3||0||8||128-256||none |- |SuperSPARC II||75-90||V8||1994||0.8||3.1||299||--||16||--||16||20||1024-2048||none |- |HyperSPARC C||125-166||V8||1995||0.35||--||--||--||--||3.3||0||8||512-1024||none |- |TurboSPARC||160-180||V8||1995||0.35||--||--||416||7||3.5||16||16||512||none |- |UltraSPARC I||143-200||V9||1995||0.5||5.2||315||521||30 @167MHz||3.3||16||16||512-1024||none |- |HyperSPARC D||180-200||V8||1996||0.35||--||--||--||--||3.3||16||16||512||none |- |UltraSPARC Two (Blackbird)||250-360||V9||1997||0.35||5.4||--||521||25 @250MHz||2.5||16||16||1024 or even 4096||none |- |UltraSPARC Two (Sapphire-Black)||360-480||V9||1999||0.25||5.4||156||521||21 @400MHz||1.9||16||16||1024-8192||none |- |UltraSPARC Trey (Sabre)||270-360||V9||1997||0.35||5.4||148||587||21||1.9||16||16||256-2048||none |- |UltraSPARC Tercet (Sapphire-Red)||333-480||V9||1998||0.25||5.4||--||587||21 @440MHz||1.9||16||16||2048||none |- |UltraSPARC IIe||400-600||V9||2000||0.Xviii Al||--||--||370||13 goop @500MHz||1.Five-One.7||16||16||256||none |- |UltraSPARC Trine (Sabre+)||550-650||V9||2002||0.Eighteen Cu||--||--||370||17.6||1.7||16||16||512||none |- |UltraSPARC III||600-900||V9||2001||0.Baker's dozen Al||29||330||1368||53||1.6||64||32||8192||none |- |UltraSPARC IIIcu||1002-1200||V9||2001||0.Xiii Cu||29||--||1368||--||1.6||64||32||8192||none |- |UltraSPARC IIIi||1064-1593||V9||2003||0.13||87.5||206||959||52||1.3||64||32||1024||none |- |UltraSPARC IV||1050-1350||V9||2004||0.13||66||356||1368||108||1.35||64||32||16384||none |- |UltraSPARC IV+||1500||V9||2005||0.09||295||336||1368||90||1.1||64||64||2048||32768 |}